The present invention is related to a method of logic simulation, and particularly to a method of logic simulation performed by a simulator.
As time goes by, the electronic devices are further minimized in size. The circuits of the electronic devices thus become more and more complicated. However, the more complicated the circuit is, the higher the possibility to arise problems in logic simulation is.
Generally, logic simulation performed by a simulator is achieved by referring to the truth tables of the logic gates. From each node state of the plural nodes of a logic circuit, the final output node state of the logic circuit can be obtained by looking up the truth tables. According to the prior art, a high potential state, a low potential state and an unknown state are defined for the plural nodes of the logic circuit. In most situations, the method of logic simulation works smoothly for the logic circuit. However, a node state can""t be identified in some specific situations.
Please refer to FIG. 1 which is a schematic diagram showing a first example of a logic circuit. In real operation of the logic circuit, as long as the node state of the input node 11 and that of the input node 13 are the high potential states, the node state of the output node 17 must be the high potential state regardless of the node state of the input node 12. However, in logic simulation performed by a simulator according to the prior art, the node state of the output node 17 can""t be identified in some specific situations. By referring to Table 1 which is a truth table of a NAND gate according to the prior art, three different situations are described more specifically as follows.
a) Given that the node state of the input node 11 and that of the input node 13 are the high potential states, and the node state of the input node 12 is the low potential state, then the node state of the node 14 is the high potential state, the node state of the node 15 is the high potential state and that of the node 16 is the low potential state. Therefore, the node state of the output node 17 is the high potential state.
b) Given that the node state of the input node 11 and that of the input node 13 are the high potential states, and the node state of the input node 12 is the high potential state, then the node state of the node 14 is the low potential state, the node state of the node 15 is the low potential state and that of the node 16 is the high potential state. Therefore, the node state of the output node 17 is the high potential state.
c) Given that the node state of the input node 11 and that of the input node 13 are the high potential states, and the node state of the input node 12 is the unknown state, then the node state of the node 14 is the unknown state, the node state of the node 15 is the unknown state and that of the node 16 is the unknown state. Therefore, the node state of the output node 17 is the unknown state.
Therefore, in logic simulation, the node state of the output node 17, i.e. the unknown state, can""t be identified in some situations. This kind of node state which can be determined in real operation of the logic circuit and can""t be identified in some situations is called xe2x80x9cfalse unknown statexe2x80x9d.
Please refer to FIG. 2 which is a schematic diagram showing a second example of a logic circuit. In real operation of the logic circuit, as long as the node state of the input node 11 and that of the input node 13 are the low potential states, the node state of the output node 17 must be the low potential state regardless of the node state of the input node 12. However, in logic simulation performed by a simulator according to the prior art, the node state of the output node 17 can""t be identified in some specific situations either.
In reality, the circuits for manufacturing electronic devices are much more complicated than the circuits depicted in FIG. 1 and FIG. 2. The possibility to arise the problem of false unknown state in logic simulation is much higher.
An object of the present invention is to provide a method of logic simulation for solving the problem of false unknown state.
According to a first aspect of the present invention, a method of logic simulation comprises the steps of defining a high potential state, a low potential state, an unknown state and a fourth state for a plurality of nodes of a logic circuit, obtaining a simulating reference according to the high potential state, the low potential state, the unknown state and the fourth state, and achieving the logic simulation according to the simulating reference.
Preferably, the logic simulation is performed by a simulator.
Preferably, the fourth state is an inverse unknown state.
Preferably, the simulating reference includes a plurality of truth tables.
Preferably, the high potential state is symbolized by xe2x80x9c1xe2x80x9d, the low potential state is symbolized by xe2x80x9c0xe2x80x9d, the unknown state is symbolized by xe2x80x9cUnxe2x80x9d and the inverse unknown state is symbolized by xe2x80x9cxcx9cUnxe2x80x9d, wherein xe2x80x9cnxe2x80x9d represents the node number of the node.
According to a second aspect of the present invention, a simulating reference of a NAND gate, adapted to be used in logic simulation, is obtained by defining a high potential state, a low potential state, an unknown state and a fourth state for a first input node, a second input node and an output node of the NAND gate.
Preferably, the simulating reference is a truth table.
Preferably, the node number of the output node is 3, the node number of the first input node is 1 and the node number of the second input node is 2.
Preferably, the fourth state is an inverse unknown state.
Preferably, the high potential state is symbolized by xe2x80x9c1xe2x80x9d, the low potential state is symbolized by xe2x80x9c0xe2x80x9d, the unknown state is symbolized by xe2x80x9cUnxe2x80x9d and the inverse unknown state is symbolized by xe2x80x9cxcx9cUnxe2x80x9d, wherein xe2x80x9cnxe2x80x9d represents a node number of the node.
Preferably, the node state of the output node is xe2x80x9cxcx9cUyxe2x80x9d when the node state of the first input node is xe2x80x9c1xe2x80x9d and that of the second input node is xe2x80x9cUyxe2x80x9d.
Preferably, the node state of the output node is xe2x80x9c1xe2x80x9d when the node state of the first input node is xe2x80x9c0xe2x80x9d and that of the second input node is xe2x80x9cUyxe2x80x9d. Preferably, the node state of the output node is xe2x80x9cUzxe2x80x9d when the node state of the first input node is xe2x80x9cUxxe2x80x9d and that of the second input node is xe2x80x9cUyxe2x80x9d if x is unequal to y.
Preferably, the node state of the output node is xe2x80x9cxcx9cUxxe2x80x9d when the node state of the first input node is xe2x80x9cUxxe2x80x9d and that of the second input node is xe2x80x9cUyxe2x80x9d if x is equal to y.
Preferably, the node state of the output node is xe2x80x9cUzxe2x80x9d when the node state of the first input node is xe2x80x9cUxxe2x80x9d and that of the second input node is xe2x80x9cxcx9cUyxe2x80x9d if x is unequal to y.
Preferably, the node state of the output node is xe2x80x9c1xe2x80x9d when the node state of the first input node is xe2x80x9cUxxe2x80x9d and that of the second input node is xe2x80x9cxcx9cUyxe2x80x9d if x is equal to y.
According to a third aspect of the present invention, a simulating reference of a NOR gate, adapted to be used in logic simulation, is obtained by defining a high potential state, a low potential state, an unknown state and a fourth state for a first input node, a second input node and an output node of the NOR gate.
Preferably, the simulating reference is a truth table.
Preferably, the node number of the output node is 3, the node number of the first input node is 1 and the node number of the second input node is 2.
Preferably, the fourth state is an inverse unknown state.
Preferably, the high potential state is symbolized by xe2x80x9c1xe2x80x9d, the low potential state is symbolized by xe2x80x9c0xe2x80x9d, the unknown state is symbolized by xe2x80x9cUnxe2x80x9d and the inverse unknown state is symbolized by xe2x80x9cxcx9cUnxe2x80x9d, wherein xe2x80x9cnxe2x80x9d represents a node number of the node.
Preferably, the node state of the output node is xe2x80x9c0xe2x80x9d when the node state of the first input node is xe2x80x9c1xe2x80x9d and that of the second input node is xe2x80x9cUyxe2x80x9d.
Preferably, the node state of the output node is xe2x80x9cxcx9cUyxe2x80x9d when the node state of the first input node is xe2x80x9c0xe2x80x9d and that of the second input node is xe2x80x9cUyxe2x80x9d.
Preferably, the node state of the output node is xe2x80x9cUzxe2x80x9d when the node state of the first input node is xe2x80x9cUxxe2x80x9d and that of the second input node is xe2x80x9cUyxe2x80x9d if x is unequal to y.
Preferably, the node state of the output node is xe2x80x9cxcx9cUxxe2x80x9d when the node state of the first input node is xe2x80x9cUxxe2x80x9d and that of the second input node is xe2x80x9cUyxe2x80x9d if x is equal to y.
Preferably, the node state of the output node is xe2x80x9cUzxe2x80x9d when the node state of the first input node is xe2x80x9cUxxe2x80x9d and that of the second input node is xe2x80x9cxcx9cUyxe2x80x9d if x is unequal to y.
Preferably, the node state of the output node is xe2x80x9c0xe2x80x9d when the node state of the first input node is xe2x80x9cUxxe2x80x9d and that of the second input node is xe2x80x9cxcx9cUyxe2x80x9d if x is equal to y.
According to a fourth aspect of the present invention, a simulating reference of a NOT (INV) gate, adapted to be used in logic simulation, is obtained by defining a high potential state, a low potential state, an unknown state and a fourth state for an input node and an output node of the NOT (INV) gate.
Preferably, the simulating reference is a truth table.
Preferably, the node number of the input node is 1 and the node number of the output node is 2.
Preferably, the fourth state is an inverse unknown state.
Preferably, the high potential state is symbolized by xe2x80x9c1xe2x80x9d, the low potential state is symbolized by xe2x80x9c0xe2x80x9d, the unknown state is symbolized by xe2x80x9cUnxe2x80x9d and the inverse unknown state is symbolized by xe2x80x9cxcx9cUxe2x80x9d, wherein xe2x80x9cnxe2x80x9d represents a node number of the node.
Preferably, the node state of the output node is xe2x80x9cxcx9cUxxe2x80x9d when the node state of the input node is xe2x80x9cUxxe2x80x9d.
Preferably, the node state of the output node is xe2x80x9cUxxe2x80x9d when the node state of the input node is xe2x80x9cxcx9cUxxe2x80x9d.